В России создан собственный компьютер ( надо брать )

+===============================
+EXPLICIT KERNEL MEMORY BARRIERS
+===============================
+
+The Linux kernel has eight basic CPU memory barriers:
+
+   TYPE      MANDATORY      SMP CONDITIONAL
+   ===============   =======================   ===========================
+   GENERAL      mb()         smp_mb()
+   WRITE      wmb()         smp_wmb()
+   READ      rmb()         smp_rmb()
+   DATA DEPENDENCY   read_barrier_depends()   smp_read_barrier_depends()
+
+General memory barriers give a guarantee that all memory accesses specified
+before the barrier will appear to happen before all memory accesses specified
+after the barrier with respect to the other components of the system.
+
+Read and write memory barriers give similar guarantees, but only for memory
+reads versus memory reads and memory writes versus memory writes respectively.
+
+Data dependency memory barriers ensure that if two reads are issued such that
+the second depends on the result of the first, then the first read is completed
+and the cache coherence is up to date before the second read is performed.  The
+primary case is where the address used in a subsequent read is calculated from
+the result of the first read:
+
+   CPU 1                      CPU 2
+   ===============   ===============
+   { a == 0, b == 1 and p == &a, q == &a }
+   ...
+   b = 2;
+   smp_wmb();
+   p = &b;               q = p;
+                         smp_read_barrier_depends();
+                         d = *q;
+
+Without the data dependency barrier, any of the following results could be
+seen:
+
+   POSSIBLE RESULT   PERMISSIBLE   ORIGIN
+   ===============   ===============   =======================================
+   q == &a, d == 0   Yes
+   q == &b, d == 2   Yes
+   q == &b, d == 1 No      Cache coherency maintenance delay
+   q == &b, d == 0   No      q read after a
+See the "Cache Coherency" section above.
+
+
+All memory barriers imply compiler barriers.
+
+Read memory barriers imply data dependency barriers.
+
+SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
+systems because it is assumed that a CPU will be apparently self-consistent,
+and will order overlapping accesses correctly with respect to itself.
+
+There is no guarantee that any of the memory accesses specified before a memory
+barrier will be complete by the completion of a memory barrier; the barrier can
+be considered to draw a line in that CPU's access queue that accesses of the
+appropriate type may not cross.
+
+There is no guarantee that issuing a memory barrier on one CPU will have any
+direct effect on another CPU or any other hardware in the system.  The indirect
+effect will be the order in which the second CPU sees the effects of the first
+CPU's accesses occur.
+
+There is no guarantee that some intervening piece of off-the-CPU hardware[*]
+will not reorder the memory accesses.  CPU cache coherency mechanisms should
+propegate the indirect effects of a memory barrier between CPUs, but may not do
+so in order (see above).